publications

2025

1. Reliability of Capacitive Read in Arrays of Ferroelectric Capacitors

   L. Fehlings, Muhtasim Alam Chowdhury, Banafsheh Saber Latibari, and 2 more authors

   In 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 2025

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   The non-destructive capacitance read-out of ferroelectric capacitors (FeCaps) based on doped HfO2 metal-ferroelectric-metal (MFM) structures offers the potential for low-power and highly scalable crossbar arrays. This is due to a number of factors, including the selector-less design, the absence of sneak paths, the power-efficient charge-based read operation, and the reduced IR drop. Nevertheless, a reliable capacitive readout presents certain challenges, particularly in regard to device variability and the trade-off between read yield and read disturbances, which can ultimately result in bit-flips. This paper presents a digital read macro for HfO2 FeCaps and provides reliability analysis for the capacitive readout of HfO2 FeCaps, taking device variability and yield challenges into account. An experimentally calibrated physics-based compact model of HfO2 FeCaps is employed to investigate the reliability of the read-out operation of the FeCap macro through Monte Carlo simulations. Based on this analysis, we identify limitations posed by the device variability and propose potential mitigation strategies through design-technology co-optimization (DTCO) of the FeCap device characteristics and the CMOS circuit design. Finally, we examine the potential applications of the FeCap macro in the context of secure hardware. We identify potential security threats and propose strategies to enhance the robustness of the system.

2. Bruno: Backpropagation Running Undersampled for Novel device Optimization

   L. Fehlings, Bojian Zhang, Paolo Gibertini, and 3 more authors

   arXiv preprint, under review in Neurocomputing, 2025

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   Recent efforts to improve the efficiency of neuromorphic and machine learning systems have fo- cused on the development of application-specific integrated circuits (ASICs), which provides hard- ware specialized for the deployment of neural networks, leading to potential gains in efficiency and performance. These systems typically feature an architecture that goes beyond the von Neumann ar- chitecture employed in general-purpose hardware such as graphic processing units (GPUs). Neural networks developed for this specialised hardware then needs to take into account the specifics of the hardware platform, which requires novel training algorithms and accurate models of the hardware, since they cannot be abstracted as a general-purpose computing platform. In this work, we present a bottom-up approach to train neural networks for hardware based on spiking neurons and synapses built on ferroelectric capacitor (FeCap) and Resistive switching non-volatile devices (RRAM) re- spectively. In contrast to the more common approach of designing hardware to fit existing abstract neuron or synapse models, this approach starts with compact models of the physical device to model the computational primitive of the neurons. Based on these models, a training algorithm is devel- oped that can reliably backpropagate through these physical models, even when applying common hardware limitations, such as stochasticity, variability, and low bit precision. The training algorithm is then tested on a spatio-temporal dataset with a network composed of quantized synapses based on RRAM and ferroelectric leaky integrate-and-fire (FeLIF) neurons. The performance of the network is compared with different networks composed of leaky integrate-and-fire (LIF) neurons. The re- sults of the experiments show the potential advantage of using BRUNO to train networks with FeLIF neurons, by achieving a reduction in both time and memory for detecting spatio-temporal patterns with quantized synapses.

2024

1. Coincidence Detection with an Analog Spiking Neuron Exploiting Ferroelectric Polarization

   Paolo Gibertini, Luca Fehlings, Thomas Mikolajick, and 3 more authors

   In 2024 IEEE International Symposium on Circuits and Systems (ISCAS), May 2024

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   The ability to detect correlated events in the environment is an important feat of biological neural networks. Neuromorphic computing strives to mimic this ability for efficient sensory processing. For this purpose, we propose a HfO2-based ferroelectric capacitor (FeCap)-complementary metal oxide semiconductor (CMOS) leaky integrate-and-fire (LIF) neuron able to detect highly correlated events exploiting two different temporal dynamics. The possibility to exploit two time constants increases the versatility of the neuron and its dynamic adaptation while offering a compact and elegant solution for detection of both transient and sustained coincidences. Moreover, the time constants are in biologically relevant time scales, which makes the neuron suitable to solve real-time tasks such as keyword spotting or sensory processing. The proposed FeCap-based LIF (FeLIF) neuron enriches the dynamic of a standard LIF neuron fostering the development of advanced event-based analog neuromorphic hardware.

2. Heracles: A HfO2 Ferroelectric Capacitor Compact Model for Efficient Circuit Simulations

   Luca Fehlings, Md Hanif Ali, Paolo Gibertini, and 4 more authors

   arXiv preprint arXiv:2410.07791, May 2024

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   This paper presents a physics-based compact model for circuit simulations in a SPICE environment for HfO2-based ferroelectric capacitors (FeCaps). The model has been calibrated based on experimental data obtained from HfO2-based FeCaps. A thermal model with an accurate description of the device parasitics is included to derive precise device characteristics based on first principles. The model incorporates statistical data that enables Monte Carlo analysis based on realistic distributions, thereby making it particularly well-suited for design-technology co-optimization (DTCO). Furthermore, the model is demonstrated in circuit simulations using an integrated circuit with current programming, wherein partial switching of the ferroelectric polarization is observed. Finally, the model was benchmarked in an array simulation, reaching convergence in 1.8 s with an array size of 100 kb.

2022

1. A Ferroelectric Tunnel Junction-based Integrate-and-Fire Neuron

   P. Gibertini, L. Fehlings, S. Lancaster, and 6 more authors

   In 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 2022

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   Event-based neuromorphic systems provide a low-power solution by using artificial neurons and synapses to process data asynchronously in the form of spikes. Ferroelectric Tunnel Junctions (FTJs) are ultra low-power memory devices and are well-suited to be integrated in these systems. Here, we present a hybrid FTJ-CMOS Integrate-and-Fire neuron which constitutes a fundamental building block for new-generation neuromorphic networks for edge computing. We demonstrate electrically tunable neural dynamics achievable by tuning the switching of the FTJ device.